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preliminary product information this document contains information for a new product. cirrus logic reserves the right to modify this product without notice. 1 copyright ? cirrus logic, inc. 2002 (all rights reserved) p.o. box 17847, austin, texas 78760 (512) 445 7222 fax: (512) 445 7581 http://www.cirrus.com cs7808 m ul t i- p u rpo s e a u dio/vid e o em b edd e d p roc e s s or features ! dual 32-bit risc processors (81 mips each) ! 32-bit dsp (81 mips) ! digital video input for picture-in-picture (pip) ! on-screen display generator ! 8-bit graphic engine with advanced vertical flicker filter ! programmable audio decoder ! mpeg1 & mpeg2 video decoder ! system interface supports atapi cd loaders and hard disk drives ! host interface supports peripherals such as 10/100 ethernet controllers, dsps, etc. ! v.90 soft-modem support ! ac'97 link support ! 2 channels of audio input ! 8 channels of audio output ! 2 channel iec60958 transmitter ! remote control input support ! large number of gpio increases design flexibility ! on-chip plls generate system clocks from 27 mhz ! sdram, sgram, and flash memory support ! available in a 208 pin mqfp description the cs7808 processor is a single chip solution that pro- vides all of the processing functions you need for a broad range of audio and video applications including thin me- dia clients, cd recorders, advanced set-top boxes, interactive tv and much more. it supports all cd for- mats, disk control, video decoding and up to eight channels of output. achieve new levels of performance with 240 highly configurable mips of processing power. its flexible set of design features maximizes perfor- mance, reduces system complexity, and minimizes system cost. cs7808 is the perfect choice. working on your next consumer entertainment product design? combine cs7808 with other cirrus mixed-sig- nal converters, dsp chips, and factory firmware for a highly integrated platform crucial for video-on-demand, set-top boxes, and other similar platforms. cs7808 is a total-e? (total entertainment) ic solution specifically designed for consumer entertainment electronics. ordering information CS7808-CM 0 to 70 c 208-pin mqfp risc-1 risc-2 memory controller 32-bit dsp video input clock manager subpicture decode audio/io host interface sdram system controls external i/os dataflow engine video processor mpeg decoder i-cache d-cache mmu mac filter scaler sdram control ram moco idct on-screen display picture-in-picture video/graphics display i-cache d-cache mmu mac flash control vlc parser dma / bitblit sram buffer remote input gpios scaler stc interupts registers i-cache x,y data memory cpu / mac pcm out pcm in xmt958 mar ?02 ds554pp1
cs7808 2 table of contents 1. characteristics and specifications ........................................................................ 5 1.1 ac and dc parametric specifications ............................................................................... 5 1.1.1 absolute maximum rating .................................................................................... 5 1.1.2 recommended operating conditions ................................................................... 5 1.1.3 electrical characteristics ...................................................................................... 6 1.2 dc characteristics ........................................................................................................... .. 7 1.2.1 host interface ........................................................................................................ 7 1.2.2 sdram interface .................................................................................................. 8 1.2.3 rom/nvram interface ...................................................................................... 10 1.2.4 video output interface ........................................................................................ 11 1.2.5 video input interface ........................................................................................... 12 1.2.6 audio input interface ........................................................................................... 13 1.2.7 audio output interface ........................................................................................ 14 1.2.8 ac97/codec interface ...................................................................................... 15 1.2.9 miscellaneous interface timing ........................................................................... 16 2. typical application ........................................................................................................ 17 3. functional description ............................................................................................... 18 3.1 block diagram ................................................................................................................ .. 18 3.2 cs7808 device details .................................................................................................... 18 3.2.1 risc-32 processors ........................................................................................... 18 3.2.2 powerful 32-bit dsp ........................................................................................... 18 3.2.3 system controls .................................................................................................. 18 3.2.4 memory controller ............................................................................................... 19 3.2.5 data flow engine ................................................................................................ 19 3.2.6 audio interface .................................................................................................... 19 3.2.7 video input .......................................................................................................... 19 3.2.8 external interface ................................................................................................ 19 3.2.9 video processor .................................................................................................. 19 3.2.10 cursor ............................................................................................................... 19 3.2.11 system functions .............................................................................................. 20 3.3 risc processor ............................................................................................................... 20 3.4 dsp processor ................................................................................................................ 20 3.5 memory control ............................................................................................................... 20 3.6 dataflow control (dma) ................................................................................................... 20 3.7 system control functions ................................................................................................ 20 contacting cirrus logic support for a complete listing of direct sales, distributor, and sales representative contacts, visit the cirrus logic web site at: http://www.cirrus.com/corporate/contacts/ preliminary product information describes products which are in production, but for which full characterization data is not yet available. advance product information de- scribes products which are in development and subject to development changes. cirrus logic, inc. has made best efforts to ensure that the information contained in this document is accurate and reliable. however, the information is subject to change without notice and is provided ?as is? without warranty of any kind (e xpress or implied). customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is curr ent and complete. all prod- ucts are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. no res ponsib ility is assumed by cirrus logic, inc. for the use of this information, including use of this information as the basis for m anufacture or sale of any items, nor for infringements of patents or other rights of third parties. this document is the property of cirrus logic, inc. and by furnishing th is information, cirrus logic, inc. grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual p roperty rights of cirrus logic, inc. cirrus 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standard i2c system.
3 cs7808 3.8 host interface ............................................................................................................... ... 21 3.9 mpeg video decoding .................................................................................................... 21 3.10 audio processing ........................................................................................................... 2 1 3.11 soft modem .................................................................................................................. .21 3.12 video ...................................................................................................................... ....... 21 4. memory map .................................................................................................................... ... 23 4.1 processor memory map .................................................................................................. 23 4.2 host port memory map .................................................................................................... 23 4.3 internal i/o space map .................................................................................................... 23 5. register description .................................................................................................... 24 5.1 cs7808 register space .................................................................................................. 24 6. pin description ............................................................................................................... .. 33 6.1 pin assignments .............................................................................................................. 34 6.2 miscellaneous interface pins ........................................................................................... 40 6.3 sdram interface ............................................................................................................. 4 1 6.4 rom/nvram interface ................................................................................................... 42 6.5 video output interface ..................................................................................................... 43 6.6 video input interface ....................................................................................................... 44 6.7 audio output/input interface ............................................................................................ 45 6.8 ac97/codec interface ................................................................................................... 46 6.9 host master/atapi interface ........................................................................................... 47 6.10 general purpose input/output (gpio) .......................................................................... 48 6.11 power and ground ........................................................................................................ 49 7. package specifications ............................................................................................... 50 list of figures figure 1. host timing diagram .................................................................................................... 7 figure 2. sdram refresh transaction ....................................................................................... 8 figure 3. sdram burst write transaction .................................................................................. 8 figure 4. sdram burst read transaction .................................................................................. 9 figure 5. sdram timing ............................................................................................................ .9 figure 6. rom/rvram timing.................................................................................................. 10 figure 7. video output timing .................................................................................................. 11 figure 8. video input timing...................................................................................................... 1 2 figure 9. audio input timings .................................................................................................... 13 figure 10. audio output timing ................................................................................................. 14 figure 11. codec timing ......................................................................................................... 15 figure 12. miscellaneous timing ............................................................................................... 16 figure 13. cs7808 typical application...................................................................................... 17 figure 14. cs7808 block diagram ............................................................................................ 18 figure 15. cs7808 pinouts........................................................................................................ 3 3 figure 16. 208-pin package drawing ........................................................................................ 50 list of tables table 1. host interface symbols / characterization data ............................................................ 7 table 2. sdram interface symbols and characterization data ................................................. 8 table 3. rom/nvram interface symbols and characterization data ...................................... 10 table 4. video output interface symbols and characterization data ....................................... 11 table 5. video input interface symbols and characterization data .......................................... 12 table 6. audio input interface symbols and characterization data .......................................... 13 table 8. ac97/codec interface symbols and characterization data ..................................... 15
cs7808 4 table 9. miscellaneous interface symbols and characterization data...................................... 16 table 10. memory map-risc0 processor ................................................................................. 23 table 11. host port memory map .............................................................................................. 23 table 12. internal i/o space map .............................................................................................. 23 table 13. cs7808 register map and blocks ............................................................................. 24 table 14. cs7808 registers ...................................................................................................... 24 table 15. pin type legend ........................................................................................................ 33 table 16. 208-pin package assignments .................................................................................. 34 table 17. miscellaneous interface pins ..................................................................................... 40 table 18. sdram interface ....................................................................................................... 41 table 19. rom/nvram interface.............................................................................................. 42 table 20. video output interface ............................................................................................... 43 table 21. video input interface .................................................................................................. 44 table 22. audio input/output interface ...................................................................................... 45 table 23. ac97/codec interface ............................................................................................. 46 table 24. host master/atapi interface ..................................................................................... 47 table 25. general purpose i/o interface ................................................................................... 48 table 26. power and ground .................................................................................................... 49
5 cs7808 1. characteristics and specifications 1.1 ac and dc parametric specifications (agnd, dgnd=0v, all voltages with respect to 0v) 1.1.1 absolute maximum rating caution: operating beyond these minimum and maximum limits can result in permanent damage to the device. cirrus logic recommends that cs7808 devices operate at the settings described in the next ta- ble. 1.1.2 recommended operating conditions symbol description min max unit vdd io power supply voltage on i/o ring -0,5 4.6 volts vdd core power supply voltage on core logic and pll -0.5 3.6 volts v i digital input applied voltage (power applied) -0.5 5.5 volts i i digital input forced current -10 10 ma i o digital output forced current -50 50 ma t sol lead soldering temperature - 260 o c t vsol vapor phase soldering temperature - 220 o c t stor storage temperature (no power applied) -40 125 o c t amb ambient temperature (power applied) 0 70 o c p total total power consumption - 2.5 w parameter symbol min typ max units supply voltage, io v dd 3.0 3.3 3.6 volts supply voltage, core and pll v dd 2.25 2.5 2.75 volts ambient temperature (power applied) t amb 02570 o c
cs7808 6 1.1.3 electrical characteristics parameter symbol conditions min typ max units supply current, io i dd normal operating - 45 - ma supply current, core and pll i dd normal operating - 550 - ma input voltage, high v ih 2.0 - 5.0 volts input voltage, low v il - - 0.8 volts input current i in v in =v dd or v ss -1 - +1 a input pull up/down resistor r i -75- k ? output voltage, high v oh @ buffer rating 2.4 - - volts output voltage, low v ol @ buffer rating - - 0.4 volts high-z leakage i oz v out =v ss or v dd -10 - +10 a input capacitance c in -3-pf
7 cs7808 1.2 dc characteristics ( t a = 25c; vdd_pll=vdd_core=2.5v10%, vdd_io=3.3v10%) 1.2.1 host interface cs7808 can interface with a atapi-type slave loader gluelessly. figure 1 illustrates a read atapi trans- action and a write atapi transaction. pio mode 4 is implemented to enable a sufficient data transfer rate between atapi device and cs7808. symbol description min typ max unit t acyc cycle time 1 1.values are guaranteed by design only. 98 ns t aavr address valid to hmrd-/hmwr- setup 10 ns t ah address hold from hmrd-/hmwr- setup 10 ns t arww h_rd-/h_wr- pulse width 72 ns t arec h_rd-/h_wr- recovery time 22 ns t awsu h_wr- data setup 20 ns t awh h_wr- data hold 10 ns t ardsu h_rd- data setup 20 ns t arddh h_rd- data hold 0 ns t arddh h_rd- data high-z 0 10 t arsu h_rdy setup time 12 ns t arh h_rdy hold time 1 0ns table 1. host interface characteristics figure 1. host timing diagram h_a[2:0] , h_cs[3:0] h_d[15:0](write) h_d[15:0](read) h_rd/h_wr t acyc t aavr t arww t ah t arec t arsu t awh t awsu t ardsu t arddh t ardts t arh h_rdy(deasserted before tarsu) h_rdy(asserted before tarsu)
cs7808 8 1.2.2 sdram interface cs7808 interfaces with either sdram or sgram for high data bandwidth transfer. figure 2 shows the refresh cycle performed by cs7808. figure 3 shows a burst write (length = 8) transaction. figure 4 on page 9 shows a burst read (length = 8) transaction, while figure 5 on page 9 shows detailed sdram in- terface timing. in both figure 3 and figure 4 ,caslatencyisprogrammedto3. symbol description min typ max unit t msur m_d[31:0] setup to m_cko 3 ns t mhr m_d[31:0] hold time after m_cko 0 ns t mco m_cko active edge to output transition 7 ns t mper m_cko period 1 1.values are guaranteed by design only. 10.5 12.2 ns t mhw m_d[31:0] valid time after m_cko 5 ns t mdow m_d[31:0] delay from m_cko rising edge 5 ns table 2. sdram interface characteristics m_cke m_a_[11:0] m_bs_n m_ras_n m_cas_n m_we_n md[31:0] m_dqm_[3:0] m_ap figure 2. sdram refresh transaction d0 d1 d2 d3 d4 d5 d6 d7 c1 c2 c3 c4 c5 c6 c7 c0 r0 m_cko m_a_[11:0] m_bs_n m_ras_n m_cas_n m_we_n m_d_[31:0] m_dqm_[3:0] m_ap figure 3. sdram burst write transaction
9 cs7808 d0 d1 d2 d3 d4 d5 d6 d7 c1 c2 c3 c4 c5 c6 c7 c0 r0 m_cko m_a_[11:0] m_bs_n m_ras_n m_cas_n m_we_n m_d_[31:0] m_dqm_[3:0] m_ap figure 4. sdram burst read transaction m_ras_n,m_cas_n m_we_n,m_ap,m_dqm[3:0], m_cke,m_a[11:0] t mper t mco m_d[31:0](write) m_d[31:0](read) m_cko t msur t mhr t mhw t mdow figure 5. sdram timing
cs7808 10 1.2.3 rom/nvram interface symbol description min typ max unit t mper m_cko period 1 1.values are guaranteed by design only. 10.5 12.2 ns t nco m_ckotoweoroeout 5 ns t nwdo m_cko to write data out 10 ns t nsur data setup to m_cko 5 ns t nhw data hold from we inactive 5 ns t nhr data hold from oe inactive 0 ns table 3. rom/nvram interface characteristics t mper t nco m_cko t nhr t nsur nvm_oe_l, nvm_we_l m_d0:15(write) t nhw t nwdo m_d0:15 (read) t nco figure 6. rom/rvram timing
11 cs7808 1.2.4 video output interface figure 7. video output timing symbol description min typ max unit t suvo vsync/hsync input setup to clk27_o 5 ns t covo1 vdat[7:0] delay from clk27_o transition 10 ns t covo2 vsync/hsync delay from clk27_o transition 10 ns t vocper clk27_o high time 1 1.values are guaranteed by design only 37.037 ns table 4. video output interface characteristics clk27_o (output) vdat[7:0] (output) vsync/hsync (output) tvocper tcovo1 tsuvo vsync/hsync (input) tcovo2
cs7808 12 1.2.5 video input interface . figure 8. video input timing symbol description min typ max unit t suvi vin_d[7:0] set up to vin_clk 5 ns t hvi vin_d[7:0] hold time after vin_clk rising edge 2 ns t vicper vin_clk high time 1 1.active clock edge is programmable. timing is referenced from active edge 37.087 ns table 5. video input interface characteristics vin_clk vin_d[7-0] t suvi t hvi t vicper vin_hsnc,vin_vsnc, vin_fld
13 cs7808 1.2.6 audio input interface symbol description min typ max units t aicl ain_bck low time 1, 2 1.values are guaranteed by design only 2.active clock edge is programmable. timing is referenced from active edge 40 50 % t aich ain_bck high time 1, 2 40 50 % t aiper ain_bck period 1, 2 216 ns t stlr time form ain_lrck transition to ain_bck active edge 5 - ns t lrts time form ain_lrck transition to ain_bck active edge 2 - ns t sdsus ain_data setup to ain_bck transition 5 - ns t sdhs ain_data hold time after ain_bck transition 2 - ns table 6. audio input interface characteristics figure 9. audio input timings ain_bck (input) ain_data (input) ain_lrck (input) t lrts t stlr t sdsus t sdhs t aich t aicl t aiper
cs7808 14 1.2.7 audio output interface symbol description min typ max units t axch aud_xclk high time (aud_xclk is input/output) 1, 2 1.values are guaranteed by design only 2.active clock edge is programmable. timing is referenced from active edge 40 50 - % t axcl aud_xclk low time (aud_xclk is input/output) 1, 2 40 50 - % t axper aud_xclk period (input/output) 1, 2 27 ns t aoper aud_bck period (output) 1, 2 216 ns t sdm aud_bck delay from aud_xclk transition - 5 ns t sdm aud_bck delay from aud_xclk transition - 3 ns t lrds aud_lrck delay from aud_bck transition - 3 ns tab le 7: audio output interface characteristics figure 10. audio output timing aud_bck(output) aud_xclk(input/output) t sdm t axch aud_bck(output) aud_do[3:0] (output) aud_lrck(output) t lrds t adsm t axcl t axper t aoperl
15 cs7808 1.2.8 ac97/codec interface figure 11. codec timing symbol description min typ max units t suc data set up to cdc_ck 5 ns t hc data hold time after cdc_ck 0 ns t coc time from active edge of cdc_ck to data transition 10 ns t cch cdc_ck high time 1, 2 1.values are guaranteed by design only 2.active clock edge is programmable. timing is referenced from active edge 40 50 % t ccl cdc_ck low time 1, 2 40 50 % t ccper cdc_ck period 1, 2 216 ns table 8. ac97/codec interface characteristics cdc_ck (intput) t suc t hc t coc t ccl t cch cdc_di, cdc_sy (input) cdc_do, cdc_sy, cdc_rst (output) t ccper
cs7808 16 1.2.9 miscellaneous interface timing symbol description min typ max units t xccper xtlclock period 1 1.xtlclock must meet the requirement of external the video encoder for correct chroma (27 mhz 1 khz). 37.037 ns t rstl reset_n pulse width 1000 ns t gpl gpio pw low 50 ns t gpl gpio pw high 50 ns table 9. miscellaneous interface characteristics reset-n t gph t gpl t rstl xtlclock gpio xccper t figure 12. miscellaneous timing
17 cs7808 2. typical application the figure 13 shows a typical example of a complete set-top box solution using the cs7808. risc-1 risc-2 audio interface external interface mpeg decoder dsp video input memory controller video processor codec daa lan controller video decoder audio dac video encoder power reg. sdram 8mb (upto32mb) flash .5-2 mb (up to 32 mb) to phone line ethernet to parallel port to audio (r) to audio (l) to rf modulator to s-video to composite video to switch to power infrared remote keyboard to led video source & tuner cs7808 figure 13. cs7808 typical application
cs7808 18 3. functional description 3.1 block diagram the cs7808 block diagram is shown in figure 14 . 3.2 cs7808 device details 3.2.1 risc-32 processors two powerful 32-bit risc processors (risc0 and risc1) virtual memory support optimizing c compiler big or little endian data formats support mac multiply/accumulate in 2 cycles with c support 4 kbyte instruction cache, 2 kbyte data cache single cycle instructions, runs at 81 mhz 3.2.2 powerful 32-bit dsp powerful 32/24-bit dsp processor 24-bit fixed point logic, with 54-bit accumulator single-cycle throughput, 2-cycle latency multiply accumulate, 34-bit simple integer logic 8-kbyte instruction cache, 8-kbyte program visible local memory single cycle instructions, runs at 81 mhz 3.2.3 system controls includes several hardware lockable semaphore registers general-purpose register for inter-processor com- munication 32-bit timers for i/o and other uses, with program- mable interval rates both hardware and software interrupts on data or debug risc0 (navigation & control) pll (main, audio, sdram) mpeg2 video decoder 2/4/8 bit osd video processor (i/o, scale, pip, mix) subpicture decoder risc1 (appl ication) ac '97 codec inter face pcm, spdif inter face audio ds p dma con trol (bitblt, css) mem control (sdram,rom) host inter face (atapi,av,isa) external io (gpio, ir ) registers data addr i2c (debug port) figure 14. cs7808 block diagram
19 cs7808 built in plls generate all required clocks from 27 mhz input clock 3.2.4 memory controller supports sdram, and sgram, from 2 mbytes to 32 mbytes supports multiple banks of flash and rom up to 16 mbytes 32-bit data bus for dram, 8 or 16-bit data bus for rom 3.2.5 data flow engine 2432 bytes of internal memory dma to/from main ram into local sram supports endian conversion and byte, short, long data formats on dma supports block transfers for graphics bit blits 3.2.6 audio interface supports pcm, i 2 s and iec-958 outputs at up to 96 khz output rate 8 output channels, 2 input channels 3.2.7 video input ntsc/pal video decoder input interface built in variable down scaling, handles ccir 601 to qcif input formats video input image can be displayed in small win- dow, or as main picture 3.2.8 external interface serial i 2 c ? master and slave port 29 independent fully programmable bi-directional i/o pins 8 edge or level detection interrupt pins hardware assisted support for infrared remote de- vices, such as remote control, infrared keyboard, mouse, printer, and more programmable parallel host master and slave inter- face supports many formats including atapi, isa, and more serial interface supports ac-97 and other standard modem codec protocols 3.2.9 video processor supports 24-bit 4:2:0 and 4:2:2 video modes and 16-bit true color graphics modes. on screen display module supports 2-bit, 4-bit, or 8- bit pixel modes, while supporting 3 separate regions and 16 transparency overlay levels picture-in-picture module includes horizontal and vertical downscaling with programmable output siz- es, positions, and borders overlay mixer with rgb to yuv conversion and output formatting supports 4:2:0, 4:2:2, yuv655, rgb565 and rgb555 frame buffer inputs outputs 4:2:2 video in ccir-601 or ccir-656 for- mat high quality scaling using a vertical and a horizontal 16 taps polyphase programmable filter and sup- ports any size image up to 768x576 programmable sharpening and de-blocking filters 5 taps programmable adaptive anti-flicker filtering for graphics source master or slave video sync configuration multiple video plains overlay (main video / video in- put / picture_in_picture / picture/on_screen / dis- play/cursor) gamma correction 3.2.10 cursor 4-bit color 16-level alpha blending
cs7808 20 3.2.11 system functions 208-pin pqfp packages all i/o pins are 3 v with 5 v tolerance advanced 0.25 micron cmos technology internal processors run at 81 mhz supports low power modes and clock shutoff 3.3 risc processor the cs7808 includes two powerful, proprietary 32-bit risc processors, risc0 and risc1, with optimizing c compiler support and source level de- bugger. the risc processors fully support many real time operation systems (rtos). in addition to being compatible with the standard mips ? r3000 ? instruction set, the risc proces- sors also have a mac engine, which performs mul- tiply/accumulate in 2 cycles in a pipelined fashion with c support, effectively achieving single cycle throughout. 3.4 dsp processor the cs7808 contains a proprietary digital signal processor (dsp), which is optimized for audio ap- plications. the dsp performs 32-bit simple integer operations, and has a 24-bit fixed point logic unit, with a 54-bit accumulator. there are 32 general- purpose registers, and eight independent address generation registers, featuring: linear and circular buffer operations, and dual operand read from memory. the multiply-accumulator has single-cy- cle throughput, with two cycle latency. the dsp is optimized for bit packing and unpacking opera- tions. the interface to main memory is designed for handling flexible block sizes and skip counts. 3.5 memory control the dram interface performs the sdram con- trol and arbitration functions for all the other mod- ules in the cs7808. the dram interface services and arbitrates a number of clients and stores their code and/or data within the local memory. this ar- bitration and scheduling guarantees the allocation of sufficient bandwidth to the various clients. the dram interface supports up to 32 mbytes. for a typical application, the cs7808 requires 8 mbytes memory space. sharing the same interface, cs7808 also supports flashrom,otp,ormaskrominterface.code is stored in rom. after the system is booted, the code is shadowed inside sdram for execution. the flash rom interface is provided so that the code can be upgraded in the field once the commu- nications channel is established (via modem port, cd-r, or serial port). utility software will be pro- vided to debug and upgrade code for the system manufacturer. 3.6 dataflow control (dma) the dma controller moves data between the exter- nal memory and internal memory. the external memory address can be specified using a register, or in fifo mode, using start and end address regis- ters. separate start/end address registers are used for dma read and write operations. the dma in- terface also has a block transfer function, which al- lows for the transfer of one block of data from one external memory location to another external mem- ory location. in effect, this feature combines a dma read and write into one operation. in addi- tion, the dma write operation allows for byte, short, word, and other types of masking. 3.7 system control functions the system control functions are used to coordinate the activities of the multiple processors, and to pro- vide the supporting system operations. four 32-bit communication registers are available for inter- processor communication, and eight semaphore registers are used for resource locking. timers are available for general-purpose functions, as well as more specialized functions such as watchdog tim- ers and performance monitoring. the large number of general purpose i/os offers flexibility in system configurations. an i 2 cmaster allows for control of other i 2 cdevices,suchasa video encoder. an i 2 c slave port shares the same pins, and can be used for debug functions. inter-
21 cs7808 rupts can be generated on specific or generic events. infrared inputs can be filtered to make them free of glitches or stored unfiltered into memory. control of all the internal clocks is also possible. internal plls are used to generate the internal sys- tem and memory clocks and audio clocks of any widely used frequency. 3.8 host interface the cs7808 has a programmable interface port which can be configured to connect to industry- standard atapi interfaces without external glue logic. the host interface can be set up in atapi mode, to connect directly to any atapi hard-disk drive (using two chip selects). 3.9 mpeg video decoding compressed mpeg data is read from internet through ethernet controller(host i/f) or soft mo- dem(codec i/f) into an input fifo in dram. the data flow (dma) controller moves video packets from the input fifo into the mpeg decod- er?s input fifo (also in dram). the dma con- troller can also perform advanced functions such as start code search, relieving the risc processors. the system synchronization function is used to control the timing of mpeg picture decoding. the mpeg video decoder processes i, b, and p frames, and writes to video frame buffers in dram for output to the display. special anti-tearing logic en- sures that currently displayed frame buffers are not overwritten. 3.10 audio processing compressed audio data is decompressed, then written to a pcm output fifo, also in dram the dma and decompression stages of audio process- ing can be done with a combination of the dma unit, dsp, and risc processors. the dsp is opti- mized for audio processing, so most common for- mats can be handled by the dsp alone, including ac-3, dts, mpeg2 audio, and mp3. the dsp has enough reserve bandwidth to handle the karaoke echo-mix and pitch shift, and ac-3 down-mix functions. the audio output data is written into a dram fifo in 16-, 18-, 20- or 24-bit pcm format. a flex- ible audio output stage can simultaneously output 8 channels of pcm data to audio dacs, or 6 chan- nels of audio data plus an iec-958 encoded output, at up to 96 khz. the audio interface also includes a flexible pcm input interface, which can input a wide range of protocols from an audio adc or an iec-958 receiver. 3.11 soft modem the soft modem processing is handled by one of the risc processors, which is typically dedicated for that function. data rates up to 56 kbits (v.90 protocol) are supported. the cs7808 interfaces to a simple external codec/daa circuit using a flexible serial interface. the serial interface is a ful- ly programmable, bi-directional interface and can be used either as a pcm interface or as an ac97 in- terface. in pcm mode, the sample size could be ad- justed to 20, 18 or 16 bits to match common dac and adc formats, or any other specific size. in ac97 mode, any slot can be used to interface either a modem codec or an audio codec. 3.12 video the digital video interface provides flexible and powerful means of outputting digital video data to external devices in ccir601/3 and ccir656 for- mats. the interface directly supports ntsc/pal video encoding, in both master and slave synchro- nization configurations. the internal frame buffer format could be 4:2:0, 4:2:2, yuv655, rgb565 and rgb555. cirrus logic provides some easy-to- use utilities in order to get the best advantage of the powerful video filtering capabilities of the cs7808. the cs7808 also features an ntsc/pal video de- coder input interface. the interface accepts ccir601, cif, and qcif formats, out of many tv decoders on the market. the video processor also
cs7808 22 allows overlay of multiple video planes (main vid- eo / video input / picture_in_picture / on_screen display / cursor). cs7808 has been proven to work with many tv encoders on the market with brands such as: crystal, brooktree, adi, and avs. the video input scaler (vis) module inputs 8-bit digital video data from a camera or pal/ntsc de- coder, optionally down-scales to sif or qsif, and stores the data in one to three dram frame buff- ers. the scaled image, with a border, can be over- laid anywhere on the screen into a ? or ?-screen sized window by the picture in picture (pip) mod- ule. an alternate method of using the video input func- tion is to input a full sized picture and present it on the screen full size (bypass mode). an internal glitch-free mux can switch the video processor clock source from the internal clock to the video input clock, allowing the pip mode to switch back and forth on the fly, with no dropout.
23 cs7808 4. memory map 4.1 processor memory map the cs7808 externally supports up to 32 mbytes dram and 16 mbytes rom/nvram. table 10 , table 11 and table 12 on the next page list the memory map as viewed by the risc processors, and identifies whether each segment is mapped or cacheable. for detailed information on programming cs7808 memory, see cs7808 memory interface user?s manual (ds525umd1). 4.2 host port memory map table11onpage23 lists the memory map as viewed by host slave port. 4.3 internal i/o space map table 10, table 11, and table 12 show how the in- ternal i/o space is mapped between general regis- ters, internal sram ports, and the risc processors? debug port. processor byte address description cacheable 0000_0000 ? 07ff_ffff dram (mapped) y 8000_0000 - 81ff_ffff dram (32 mbytes) y 9400_0000 ? 9cff_ffff 16-bit nvram write (16 mbytes) n 9c00_0000 ? 9cff_ffff 16-bit nvram/rom (16 mbytes) y 9d00_0000 ? 9dff_ffff 8-bit nvram/rom (16 mbytes) y a000_0000 ? a1ff_ffff dram (32 mbytes) n b000_0000 ? b003_ffff internal i/o (256 kbytes) n b400_0000 ? bcff_ffff 16-bit nvram write (16 mbytes) n bc00_0000 ? bcff_ffff 16-bit nvram/rom (16 mbytes) n bd00_0000 ? bdff_ffff 8-bit nvram/rom (16 mbytes) n c000_0000 ? ffff_ffff dram (mapped) y table 10. memory map-risc0 processor host byte address description 0000 0000 ? 003f ffff internal i/o space 1000 0000 ? 13ff ffff dram space (16 mbytes) 1400 0000 ? 17ff ffff nvram space (16 mbytes) table 11. host port memory map byte address offset description 0_0000 ? 0_2fff general registers 0_3000 ? 1_ffff general internal sram 2_0000 ? 2_ffff risc_0 internal sram/registers 3_0000 ? 3_ffff risc_1 internal sram/registers table 12. internal i/o space map
cs7808 24 5. register description 5.1 cs7808 register space table 13 lists the register groups, and how they are split among the main cs7808 functional blocks. table 14 lists all the registers for the cs7808 and their addresses, and indicates whether the registers are read/write (r/w), read only (ro), or write only (wo). cs7808 register block 000xx, 010xx general 001xx host 002xx drc 003xx dma 005xx serial interface 006xx dsp 007xx synchronization control 008xx mpeg video decoder 009xx video input scaler 00axx picture-in-picture 00bxx video processor 00cxx subpicture display 00dxx on-screen display 00exx pcm in/out 02xxxx risc_0 03xxxx risc_1 table 13. cs7808 register map and blocks address type function register name 000 r/w general command 010 r/w general interproc_comm_register_0 014 r/w general interproc_comm_register_1 018 r/w general interproc_comm_register_2 10c r/w general interproc_comm_register_3 020 r/w general semaphore_register_0 024 r/w general semaphore_register_1 028 r/w general semaphore_register_2 02c r/w general semaphore_register_3 030 r/w general semaphore_register_4 034 r/w general semaphore_register_5 038 r/w general semaphore_register_6 table 14. cs7808 registers
25 cs7808 03c r/w general semiphore_register_7 040 ro general genio_read_data 044 r/w general genio_write_data 048 r/w general genio_three_state_enable 04c r/w general genio_positive_edge 050 r/w general genio_negative_edge 054 r/w general genio_interrupt_status 058 r/w general genio_positive_edge_mask 05c r/w general genio_negative_edge_mask 060 r/w general genio_level_mask 064 r/w general genio_mode register 1040 ro general geniomis_read_data 1044 r/w general geniomis_write_data 1048 r/w general geniomis_three_state_enable 104c r/w general geniomis_positive_edge 1050 r/w general geniomis_negative_edge 1054 r/w general geniomis_interrupt_status 1058 r/w general geniomis_positive_edge_mask 105c r/w general geniomis_negative_edge_mask 1060 r/w general geniomis_level_mask 1064 r/w general geniomis_mode register 1068 ro general geniod_read_data 106c r/w general geniod_write_data 1070 r/w general geniod_hiz_state_enable 1074 ro general geniohst_read_data 1078 r/w general geniohst_write_data 107c r/w general geniohst_hiz_state_enable 068 r/w general i 2 c_mstr_read_comand 06c r/w general i 2 c_mstr_write_1byte 070 r/w general i 2 c_mstr_write_2bytes 074 r/w general i 2 c_mstr_control 078 ro general i 2 c_mstr_status 07c ro general i 2 c_mstr_read_data 080 r/w general rsk0_interrupt_mask 084 wo general rsk0_interrupt_set 088 r/w general rsk0_interrupt_status 08c ro general rsk0_interrupt_cause 090 r/w general dsp_interrupt_mask 094 wo general dsp_interrupt_set address type function register name table 14. cs7808 registers (continued)
cs7808 26 098 r/w general dsp_interrupt_status 09c ro general dsp_interrupt_cause 0a0 r/w general rsk0_interrupt_mask2 0a4 wo general rsk0_interrupt_set2 0a8 r/w general rsk0_interrupt2_status 0ac ro general rsk0_interrupt_cause2 1080 r/w general rsk1_interrupt_mask 1084 wo general rsk1_interrupt_set 1088 r/w general rsk1_interrupt_status 108c ro general rsk1_interrupt_cause 10a0 r/w general rsk1_interrupt_mask2 10a4 wo general rsk1_interrupt_set2 10a8 r/w general rsk1_interrupt2_status 10ac ro general rsk1_interrupt_cause2 0b0 r/w general dsp_interrupt_mask2 0b4 wo general dsp_interrupt_set2 0b8 r/w general dsp_interrupt2_status 0bc ro general dsp_interrupt_cause2 0c0 r/w general timer_0 0c4 r/w general timer_1 0c8 r/w general timer_2 0cc r/w general timer_3 0d0 r/w general timer_control 0d4 ro general performance_monitor_count 0d8 r/w general timer_m_over_n 0e0 r/w general ir_control 0e4 r/w general ir_dram_start_address 0e8 r/w general ir_dram_end_address 0ec ro general ir_dram_write_address 0f0 r/w general pll_control_register1 10f0 r/w general low_power_clock_control 0f4 r/w general pll_control_register2 10f4 r/w general pll_control_register3 0f8 r/w general pll_turn_off 0fc r/w general pll_clock_divider 100 r/w host device_1_control 104 r/w host device_2_control 108 r/w host device_3_control 10c r/w host device_4_control 110 r/w host write_data_port address type function register name table 14. cs7808 registers (continued)
27 cs7808 114 ro host read_data_port 120 r/w host host_start_address 124 r/w host dram start address 128 r/w host stream_transfer_size 12c r/w host dram_burst_threshold 13c r/w host host_master_control 200 r/w dram controller dram_controller_priority0 204 r/w dram controller dram_controller_priority1 208 r/w dram controller dram_controller_priority2 20c r/w dram controller dram_controller_priority3 210 r/w dram controller dram_controller_priority4 214 r/w dram controller dram_controller_setup 218 r/w dram controller dram_command 21c r/w dram controller dram_controller_mb_width 220 r/w dram controller dram_controller_debug_control 224 ro dram controller dram_debug_status 300 wo dma dma_enable 304 r/w dma dma_control 308 ro dma dma_status 30c r/w dma xfer_byte_cnt 310 r/w dma dram_byte_start_addr 314 r/w dma sram_byte_start_addr 318 r/w dma fifo_start_rd_addr 31c r/w dma fifo_start_wr_addr 328 r/w dma search_control 32c ro dma search_status 330 r/w dma fifo_end_rd_addr 334 r/w dma fifo_end_wr_addr 338 r/w dma lines_and_skip 33c r/w dma byte_mask_pattern 540 r/w ser/dci serial_frame_sync_control 544 r/w ser/dci serial_output_input_control 548 r/w ser/dci ac97_codec_control 54c r/w ser/dci ac97_codec_command 550 r/w ser/dci serial_output_fifo_start_address 554 r/w ser/dci serial_output_fifo_end_address 558 r/w ser/dci serial_input_fifo_start_address 55c r/w ser/dci serial_input_fifo_end_address 560 ro ser/dci serial_output_fifo_read_address 564 ro ser/dci serial_input_fifo_write_address address type function register name table 14. cs7808 registers (continued)
cs7808 28 568 r/w ser/dci serial_clock_synthesis_parameters 56c ro ser/dci codec_register_status 570 r/w ser/dci slot5_register_data 574 r/w ser/dci slot10_register_data 578 r/w ser/dci slot11_register_data 57c r/w ser/dci slot12_register_data 580 r/w ser/dci out_fifo_int 584 r/w ser/dci in_fifo_int 588 r/w ser/dci rate_control 600 wo dsp dsp_boot_code_start_address 604 wo dsp dsp_run_enable 6xx ro dsp dsp_program_cntrun_status 700 r/w synchronization control audio_sync_control 704 r/w synchronization control video_sync_control 708 ro synchronization control video_sync_status 70c r/w synchronization control wait_line 710 r/w synchronization control frame_period 714 r/w synchronization control stc_interval 718 r/w synchronization control system_time_clock 71c r/w synchronization control top_bits 720 r/w synchronization control video_pts_fifo_start_address 724 r/w synchronization control video_pts_fifo_end_address 728 r/w synchronization control video_pts_fifo_write_address 72c ro synchronization control video_pts_fifo_read_address 730 r/w synchronization control subpicture_pts_fifo_start_address 734 r/w synchronization control subpicture_pts_fifo_end_address 738 r/w synchronization control subpicture_pts_fifo_write_address 73c ro synchronization control subpicture_pts_fifo_read_address 740 r/w synchronization control highlight_start_pts 744 r/w synchronization control highlight_end_pts 748 r/w synchronization control button_end_pts 74c rw synchronization control highlight_control_information_address 750 r/w synchronization control video_pts 754 r/w synchronization control audio_pts 758 ro synchronization control subpicture_pts 75c ro synchronization control audio_time 760 ro synchronization control video_sync_debug 764 r/w synchronization control sp_drc_vpts_debug 768 r/w synchronization control frame_count_interrupt 76c r/w synchronization control video_dts address type function register name table 14. cs7808 registers (continued)
29 cs7808 770 ro synchronization control sync_interrupt_status 774 r/w synchronization control sync_interrupt_control 778 wo synchronization control sync_interrupt_set 77c wo synchronization control sync_interrupt_clear 800 r/w mpeg video decoder mpeg_video_control 804 r/w mpeg video decoder mpeg_video_setup 808 r/w mpeg video decoder mpeg_video_fifo_start_address 80c r/w mpeg video decoder mpeg_video_fifo_end_address 810 ro mpeg video decoder mpeg_video_fifo_current_address 814 ro mpeg video decoder mpeg_video_horiz_pan_vector 818 wo mpeg video decoder mpeg_video_fifo_add_bytes 81c ro mpeg video decoder mpeg_video_fifo_curr_bytes 820 r/w mpeg video decoder mpeg_video_fifo_interrupt_bytes 824 ro mpeg video decoder mpeg_video_fifo_total_bytes 828 ro mpeg video decoder mpeg_video_status 82c r/w mpeg video decoder macroblock width_height 830 ro mpeg video decoder mpeg_video_debug 834 r/w mpeg video decoder mpeg_u_offset 83c r/w mpeg video decoder mpeg_i_base_register 840 r/w mpeg video decoder mpeg_p_base_register 844 r/w mpeg video decoder mpeg_dest_control 848 ro mpeg video decoder mpeg_software_flags 84c r/w mpeg video decoder mpeg_v_offset 854 r/w mpeg video decoder mpeg_antitearwindow 858 r/w mpeg video decoder mpeg_error_pos 900 r/w video input scaler vis_control 904 r/w video input scaler vis_startx 908 r/w video input scaler vis_endx 90c r/w video input scaler vis_starty 910 r/w video input scaler vis_endy 914 r/w video input scaler vis_frame_base 918 r/w video input scaler vis_u_offset 91c r/w video input scaler vis_v_offset 920 r/w video input scaler vis_frame_size a00 r/w picture-in-picture pip_control a04 r/w picture-in-picture pip_vidbrdstartx a08 r/w picture-in-picture pip_vidbrdendx a0c r/w picture-in-picture pip_vidbrdstarty a10 r/w picture-in-picture pip_vidbrdendy a14 r/w picture-in-picture pip_borderclr address type function register name table 14. cs7808 registers (continued)
cs7808 30 a18 r/w picture-in-picture pip_vscale a1c r/w picture-in-picture pip_line_offnum_bot a20 r/w picture-in-picture pip_frbasey a24 r/w picture-in-picture pip_frbaseu a28 r/w picture-in-picture pip_frbasev a2c r/w picture-in-picture pip_line_width a30 r/w picture-in-picture pip_ line_offnum_top a34 r/w picture-in-picture pip_frame_size b00 r/w video processor video_processor_control b04 r/w video processor video_dram_line_length b08 r/w video processor display_activex b0c r/w video processor display_activey b10 r/w video processor blank_color b14 r/w video processor internal_hsync_count b18 r/w video processor internal_vsync_count b1c r/w video processor horizontal_y_offset b20 r/w video processor horizontal_uv_offset b24 r/w video processor vertical_offset b28 r/w video processor video_line_size b2c r/w video processor frame_buffer_base b30 r/w video processor video_line_mode_buffer b34 r/w video processor horizontal_vertical_filter b38 r/w video processor source_x_offset b3c r/w video processor horizontal_video_scaling b40 r/w video processor frame_v_buffer_compressed_offset b44 wo video processor mb_width b48 wo video processor anti-flicker b4c wo video processor anti-flicker b50 wo video processor anti-flicker b54 wo video processor anti-flicker b58 wo video processor anti-flicker b5c wo video processor gamma control b60 wo video processor gamma control b64 wo video processor gamma control b68 wo video processor gamma control b6c wo video processor gamma control b70 wo video processor gamma control b74 wo video processor gamma control b78 wo video processor gamma control b7c r/w video processor vid_sync adjust address type function register name table 14. cs7808 registers (continued)
31 cs7808 c00 r/w subpicture subpicture_color0 c04 r/w subpicture subpicture_color1 c08 r/w subpicture subpicture_color2 c0c r/w subpicture subpicture_color3 c10 r/w subpicture subpicture_color4 c14 r/w subpicture subpicture_color5 c18 r/w subpicture subpicture_color6 c1c r/w subpicture subpicture_color7 c20 r/w subpicture subpicture_color8 c24 r/w subpicture subpicture_color9 c28 r/w subpicture subpicture_color10 c2c r/w subpicture subpicture_color11 c30 r/w subpicture subpicture_color12 c34 r/w subpicture subpicture_color13 c38 r/w subpicture subpicture_color14 c3c r/w subpicture subpicture_color15 c40 r/w subpicture subpicture_dci_address c44 r/w subpicture subpicture_hli_address c50 r/w subpicture subpicture_control c54 r/w subpicture subpicture_display_offset c58 r/w subpicture subpicture_display_scale d00 ro on screen display osd_status d04 r/w on screen display osd_control d08 r/w on screen display osd_color_number d0c r/w on screen display osd_color_data d10 r/w on screen display osd_region1_control d14 r/w on screen display osd_region1_hlimits d18 r/w on screen display osd_region1_vlimits d1c r/w on screen display osd_region1_drambase d20 r/w on screen display osd_region2_control d24 r/w on screen display osd_region2_hlimits d28 r/w on screen display osd_region2_vlimits d2c r/w on screen display osd_region2_drambase d30 r/w on screen display osd_region3_control d34 r/w on screen display osd_region3_hlimits d38 r/w on screen display osd_region3_vlimits d3c r/w on screen display osd_region3_drambase d40 r/w on screen display osd_blend d44 r/w on screen display osd_debug1 d48 r/w on screen display osd_debug2 address type function register name table 14. cs7808 registers (continued)
cs7808 32 e00 r/w pcm pcm_run_clear e04 r/w pcm pcm_output_control e08 r/w pcm pcm_out_fifo_start_address e0c r/w pcm pcm_out_fifo_end_address e10 r/w pcm pcm_out_fifo_interrupt_address e14 ro pcm pcm_out_fifo_current_address e18 r/w pcm spdif_channel_status e20 r/w pcm pcm_input_control e24 r/w pcm pcm_in_fifo_start_address e28 r/w pcm pcm_in_fifo_end_address e2c r/w pcm pcm_in_fifo_interrupt_address e30 r/w pcm pcm_out_fifo_interrupt_address2 e34 r/w pcm pcm_out_fifo_interrupt_address3 e38 ro pcm pcm_in_fifo_current_address e3c rw pcm spdif_output_control e40 rw pcm spdif_output_fifo_start_address e44 rw pcm spdif_output _fifo_end_address e48 ro pcm spdif_output _fifo_current_address e4c rw pcm spdif_output _fifo_interrupt_address e50 rw pcm spdif_output_add_block 2xxxx r/w risc0 risc 0 processor registers 3xxxx r/w risc1 risc 1 processor registers address type function register name table 14. cs7808 registers (continued)
33 cs7808 6. pin description table 15 lists the conventions used to identify the pin type and direction. pin type direction i input is input, with schmitt trigger id input, with pull down resistor iu input, with pull up resistor ooutput o4 output ? 4madrive o8 output ? 8madrive t4 high-z output ? 4ma drive b bi-direction b4 bi-direction ? 4madrive b4u bi-direction ? 4madrive,withpull-up b8u bi-direction ? 8madrive,withpull-up b4s bi-direction ? 4 ma drive, with schmitt trigger b4su bi-direction ? 4 ma drive, with pull-up and schmitt trigger pwr +2.5 v or +3.3 v power supply voltage gnd power supply ground name_n low active table 15. pin type legend h_d[15:0] h_cs[3:0] h_a[4:0] h_ale h_rd h_wr h_cko h_rdy vin_ d[7:0] vin_hsnc vin_vsnc vin_clk vin_fld m_a[11:0] m_bs_n m_d[31:0] m_dqm_[3:0] m_ras_n m_cas_n m_we_n m_ap m_cke m_cko nvr_oe_n nvr_wr_n hsync vsync clk27_o vdat[7:0] aud_bck aud_lrck aud_do[3:0] ain_bck ain_lrck ain_data cdc_di cdc_do cdc_rst cdc_ck cdc_sy gpio _ d[20-0] ir_in mfg_tst xtlclock rst_n cs7808 host interface (30) video in (12) memory if (57) video out (11) dac out (7) misc. (41) codec if (5) adc in (3) spdif_o gpio _ h[16-14] gpio_v10 gpio_[15-10, 8-7, 4-2, 0] scl sda figure 15. cs7808 pinouts
cs7808 34 6.1 pin assignments table 16 lists the pin number, pin name, and pin type for the 208 pin cs7808 package. the primary func- tion and pin direction is shown for all signal pins. for some signal pins, a secondary function and direction are also shown. for pins having more than one function, the primary function is chosen when the chip is reset. pin name type primary function dir secondary function dir note 1 vdd_pll pwr pll power 2.5v i 2 m_a_11 o8 sdram address[11] o rom/nvram address[11] o 3 m_a_10 o8 sdram address[10] o rom/nvram address[10] o 4 gpio_d18 b4u geniod[18] b system clock pll bypass i 5 m_a_9 o8 sdram address[9] o rom/nvram address[9] o 6 m_a_8 o8 sdram address[8] o rom/nvram address8] o 7 m_a_7 o8 sdram address[7] o rom/nvram address[7] o 8 gpio_d16 b4su geniod[16] b 9 m_a_6 o8 sdram address[6] o rom/nvram address[6] o 10 m_a_5 o8 sdram address[5] o rom/nvram address[5] o 11 m_a_4 o8 sdram address[4] o rom/nvram address[4] o 12 gpio_d17 b4u geniod[17] b 13 m_a_3 o8 sdram address[3] o rom/nvram address[3] o 14 m_a_2 o8 sdram address[2] o rom/nvram address[2] o 15 m_a_1 o8 sdram address[1] o rom/nvram address[1] o 16 m_a_0 o8 sdram address[0] o rom/nvram address[0] o 17 gpio_d19 b4u geniod[19] b memory clock pll bypass i 18 vss_io gnd i/o ground i 19 m_cko o8 sdram clock o 20 vdd_io pwr i/o power 3.3v i 21 m_bs_n o8 sdram bank select o 22 m_cke b8 sdram clock enable o geniomis(7) b 3 23 m_ap o8 sdram auto pre-charge o 24 m_ras_n o8 sdram row strobe o 25 m_cas_n o8 sdram column strobe o 26 gpio_d20 b4u geniod[20] b 27 m_we_n o8 sdram write enable o 28 m_dqm_0 o8 sdram dqm[0] o 29 m_dqm_1 o8 sdram dqm[1] o 30 gpio_d0 b4u geniod[0] b 31 m_dqm_2 o8 sdram dqm[2] o 32 m_dqm_3 o8 sdram dqm[3] o 33 m_d_8 b8u sdram data[8] b rom/nvram data[8] b 34 gpio_d1 b4u geniod[1] b table 16. 208-pin package assignments
35 cs7808 35 vss_io gnd i/o ground i 36 vss_core gnd core ground i 37 m_d_7 b8u sdram data[7] b rom/nvram data[7] b 38 vdd_io pwr i/o power 3.3v i 39 gpio_d2 b4u geniod[2] b 40 m_d_9 b8u sdram data[9] b rom/nvram data[9] b 41 vdd_core pwr core power 2.5v i 42 m_d_6 b8u sdram data[6] b rom/nvram data[6] b 43 gpio_d3 b4u geniod[3] b 44 m_d_10 b8u sdram data[10] b rom/nvram data[10] b 45 m_d_5 b8u sdram data[5] b rom/nvram data[5] b 46 m_d_11 b8u sdram data[11] b rom/nvram data[11] b 47 gpio_d4 b4u geniod[4] b 48 m_d_4 b8u sdram data[4] b rom/nvram data[4] b 49 m_d_12 b8u sdram data[12] b rom/nvram data[12] b 50 gpio_d5 b4u geniod[5] b 51 m_d_3 b8u sdram data[3] b rom/nvram data[3] b 52 unused may leave unconnected 53 unused may leave unconnected 54 m_d_13 b8u sdram data[13] b rom/nvram data[13] b 55 m_d_2 b8u sdram data[2] b rom/nvram data[2] b 56 m_d_14 b8u sdram data[14] b rom/nvram data[14] b 57 gpio_d6 b4u geniod[6] b 58 vss_io gnd i/o ground i 59 m_d_1 b8u sdram data[1] b rom/nvram data[1] b 60 m_d_15 b8u sdram data[15] b rom/nvram data[15] b 61 gpio_d7 b4u geniod[7] i b 62 m_d_0 b8u sdram data[0] b rom/nvram data[0] b 63 vss_core gnd core ground i 64 m_d_24 b8u sdram data[24] b rom/nvram address[20] o 2 65 gpio_d11 b4u geniod[11] b 66 vdd_core pwr core power 2.5v i 67 m_d_23 b8u sdram data[23] b rom/nvram address[19] o 2 68 m_d_25 b8u sdram data[23] b rom/nvram address[21] o 2 69 gpio_d10 b4u geniod[10] b 70 m_d_22 b8u sdram data[22] b rom/nvram address[18] o 2 71 m_d_26 b8u sdram data[26] b rom/nvram address[22] o 2 72 m_d_21 b8u sdram data[21] b rom/nvram address[17] o 2 73 gpio_d9 b4u geniod[9] b 74 m_d_27 b8u sdram data[27] b rom/nvram address[23] o 2 pin name type primary function dir secondary function dir note table 16. 208-pin package assignments (continued)
cs7808 36 75 m_d_20 b8u sdram data[20] b rom/nvram address[16] o 2 76 m_d_28 b8u sdram data[28] b 2 77 gpio_d8 b4u geniod[8] b 78 m_d_19 b8u sdram data[19] b rom/nvram address[15] o 2 79 m_d_29 b8u sdram data[29] b 2 80 m_d_18 b8u sdram data[18] b rom/nvram address[14] o 2 81 nv_we_n b4u nvram write enable o geniomis[8] b 82 vss_core gnd core ground i 83 m_d_30 b8u sdram data[30] b rom/nvram decode low o 2 84 vdd_core pwr core power 2.5v i 85 h_ale b4u host address latch o geniohst[13] b 86 m_d_17 b8u sdram data[18] b rom/nvram address[13] o 2 87 m_d_31 b8u sdram data[31] b rom/nvram decode high o 2 88 m_d_16 b8u sdram data[16] b rom/nvram address[12] o 2 89 gpio_h14 b4u geniohst[14] b 90 nv_oe_n o4 rom/nvram output enable o 91 vdd_io pwr i/o power 3.3v i 92 h_rd b4s host read strobe o i 93 h_wr b4 host write strobe o i 94 gpio_h15 b4u geniohst[15] b 95 h_rdy b4 host ready i o 96 vss_io gnd i/o ground i 97 h_a_2 b4 host address[2] o geniohst[10] b 98 gpio_h16 b4u geniohst[16] b 99 h_a_1 b4 host address[1] o geniohst[9] b 100 h_a_0 b4 host address[0] o geniohst[8] b 101 h_cs_1 b4 host chip select [1] o i 102 h_a_4 b4 host address[4] o geniohst[12] b 103 vss_core gnd core ground i 104 vss_pll gnd pll ground i 105 vdd_pll pwr pll power 2.5v i 106 h_cs_0 b4 host chip select[0] o i 107 h_a_3 b4 host address[3] o geniohst[11] b 108 vdd_core pwr core power 2.5v i 109 h_d_15 b4 host data[15] b i 1 110 h_d_14 b4 host data[14] b i 1 111 h_cs_3 b4 host chip select[3] o geniohst[18] b 112 h_d_13 b4s host data[13] b i 1 113 h_d_12 b4 host data[12] b i 1 pin name type primary function dir secondary function dir note table 16. 208-pin package assignments (continued)
37 cs7808 114 h_d_11 b4 host data[11] b i 2 115 h_cs_2 b4 host chip select[2] o geniohst[17] b 116 h_d_10 b4 host data[10] b o 2 117 h_d_9 b4 host data[9] b i 2 118 h_d_8 b4 host data[8] b o 2 119 vss_io gnd i/o ground i 120 h_cko b4 host clock o geniohst[19] b 121 h_d_7 b4 host data[7] b i 122 h_d_6 b4 host data[6] b i 123 h_d_5 b4 host data[5] b i 124 aud_bck b4 audio out bit clock o geniomis[3] b 3 125 h_d_4 b4 host data[4] b i 126 vss_core gnd core ground i 127 h_d_3 b4 host data[3] b i 128 aud_lrck o4 audio out lr clock o 129 vdd_core pwr core power 2.5v i 130 h_d_2 b4 host data[2] b i 131 vdd_io pwr i/o power 3.3v i 132 h_d_1 b4 host data[1] b i 133 aud_do_2 b4 audio out data[2] o geniomis[2] b 3 134 h_d_0 b4 host data[0] b i 135 aud_do_0 o4 audio out data[0] o 136 aud_do_1 b4 audio out data[1] o geniomis[1] b 3 137 ain_bck iu audio in bit clock i 138 vss_core gnd core ground i 139 ain_lrck iu audio in lr clock i 140 ain_data b4u audio in data i geniomis[0] b 3 141 vdd_core pwr core power 2.5v i 142 cdc_di iu serial codec data in i 143 vss_io gnd i/o ground i 144 cdc_do t4 serial codec data out o 145 vin_clk iu video input clock i 146 cdc_rst t4 serial codec reset o 147 cdc_ck iu serial codec bit clock i 148 cdc_sy b4u serial codec sync b 149 gpio_v10 b4u geniomis[26] b 150 gpio_d15 b4u geniod[15] b 151 gpio_d14 b4u geniod[14] b 152 gpio_d13 b4su geniod[13] b 153 vin_vsnc b4u video input vsync i geniomis[25] b pin name type primary function dir secondary function dir note table 16. 208-pin package assignments (continued)
cs7808 38 154 clk27_o b4u video output clock o geniomis[6] b 155 gpio_d12 b4u geniod[12] b 156 vdd_pll pwr pll power 2.5v i 157 vss_pll gnd pll ground i 158 vss_core gnd core ground i 159 hsync b4u video output hsync o geniomis[4] b 160 vin_hsync b4u video input hsync i geniomis[24] b 161 vdd_core pwr core power 2.5v i 162 vsync b4u video output vsync o geniomis[5] b 163 vdat_0 o4 video output data[0] o 164 vin_d0 b4u video input data[0] i geniomis[16] b 165 vdat_1 o4 video output data[1] o 166 vdat_2 o4 video output data[2] o 167 vdat_3 o4 video output data[3] o 168 vin_d1 b4u video input data[1] i geniomis[17] b 169 vdat_4 o4 video output data[4] o 170 vdat_5 o4 video output data[5] o 171 unused may leave unconnected 172 vdat_6 o4 video output data[6] o 173 vdat_7 o4 video output data[7] o 174 gpio_0 b4u general purpose io[0] b audio pll input bypass i 175 vin_d2 b4u video input data[2] i geniomis[18] b 176 vss_core gnd core ground i 177 aud_do_3 b4u audio out data[3] o general purpose io[1] b 178 vdd_core pwr core power 2.5v i 179 vin_d3 b4u video input data[3] i geniomis[19] b 180 vdd_io pwr i/o power 3.3v i 181 gpio_2 b4u general purpose io[2] b 182 vss_io gnd i/o ground i 183 gpio_3 b4u general purpose io[3] b 184 vin_d4 b4u video input data[4] i geniomis[20] b 185 gpio_4 b4u general purpose io[4] b 186 scl b4u i 2 c clock b general purpose io[5] b 187 sda b4u i 2 c data b general purpose io[6] b 188 gpio_7 b4u general purpose io[7] b 189 vin_d5 b4u video input data[5] i geniomis[21] b 190 gpio_8 b4u general purpose io[8] b 191 aud_xclk b4u audio 256x/384x clock b general purpose io[9] b 192 gpio_10 b4u general purpose io[10] b 193 vin_d6 b4u video input data[6] i geniomis[22] b pin name type primary function dir secondary function dir note table 16. 208-pin package assignments (continued)
39 cs7808 notes: 1. m_d[31:16] are driving when cs7808 is reading rom/nvram on m_d[15:0], which occurs immediately after reset. 2. h_d(15:8) pins may be reassigned as geniohst(7:0) 3. pin can receive level or edge signals which generate an internal interrupt if pin is used as gpio 194 gpio_11 b4u general purpose io[11] b 195 gpio_12 b4u general purpose io[12] b 196 gpio_13 b4u general purpose io[13] b 197 gpio_14 b4u general purpose io[14] b 198 vin_d7 b4u video input data[7] i geniomis[23] b 199 gpio_15 b4u general purpose io[15] b 200 vss_core gnd core ground i 201 ir_in is infrared input i 202 xtlclock i 27 mhz clock in i 203 vdd_core pwr core power 2.5v i 204 spdif_o o4 s/pdif out o 205 reset_n is reset in i 206 mfg_test i (tie to ground) i 207 vin_fld id video input field i 208 vss_pll gnd pll ground i pin name type primary function dir secondary function dir note table 16. 208-pin package assignments (continued)
cs7808 40 6.2 miscellaneous interface pins these pins are used for used for basic functions such as clock and reset input. see table 17 . the i 2 cpins are used for both master and slave mode (8-bit slave address is 0x30 for write, and 0x31 for read). pin signal name type description 186 scl b i 2 cclock 187 sda b i 2 cdata 201 ir_in i infrared input, from ir receiver. 202 xtlclock i 27 mhz clock input. 205 reset_n i reset input, active low. 206 mfg_test i manufacturing test pin, should always connect to ground. table 17. miscellaneous interface pins
41 cs7808 6.3 sdram interface these pins are used to interface the cs7808 with some external sdram. the cs7808 can interface with sdram of various sizes. both 16 and 32-bit data width is supported, but best performance is achieved with 32 bits. follow the instructions in table 18 on how to interface with any particular configuration of sdram. pin signal name type description 87, 83, 79, 76, 74, 71, 68, 64, 67, 70, 72, 75, 78, 80, 86, 88, 60, 56, 54, 49, 46, 44, 40, 33, 37, 42, 45, 48, 51, 55, 59. 62 m_d[31..0] b memory data bus. cs7808 can use all 32 bits or can use only m_d[15..0], in which case m_d[31..16] can be left un-con- nected. 2, 3, 5, 6, 7, 9, 10, 11, 13, 14, 15, 16 m_a[11..0] o memory address bus. connect in order starting with m_a[0] to all ram address pins not already connected to m_bs_l or m_ap. unused upper m_a pins unconnected. 19 m_cko o memory clock 22 m_cke o memory clock enable 21 m_bs_n o bank selection. always connect to ram bs or bs0 pin. 23 m_ap o memory auto pre-charge. always connect to ram ap pin. 24 m_ras_n o memory row address strobe 25 m_cas_n o memory column address strobe 27 m_we_n o memory write enable 32, 31, 29, 28 m_dqm[3..0] o io mask of data bus m_dqm[3] -> m_d[31:24] table 18. sdram interface
cs7808 42 6.4 rom/nvram interface this is the interface to the non-volatile memory that contains the firmware. see table 19 . it could be either rom, nvram ? flash, or eeprom, or any combination of these types of memory. this interface can also connect to sram that would emulate a rom on a development system. the bus width is 8 or 16 bits. except for the nvm_we_n and nvm_oe_n pins, all these pins are shared with the dram interface, which operates simultaneously with the rom/nvram interface. pin signal name type description 60, 56, 54, 49, 46, 44, 40, 33, 37, 42, 45, 48, 51, 55, 59. 62 m_d[15..0] b memory data bus. use m_d[7:0] for 8-bit interface 2, 3, 5, 6, 7, 9, 10, 11, 13, 14, 15, 16 m_a[11..0] o memory address bus[11..0] 74, 71, 68, 64, 67, 70, 72, 75, 78, 80, 86, 88 m_d[27..16] o memory address bus[23..12] for 16-bit data mode, m_d[26:16] is upper word address. for 8-bit data mode, m_d[27:16] is upper byte address. 83 m_d[30] o address decode low. copy of address msb. 87 m_d[31] o address decode high. compliment of address msb. 60 nvm_we_n o nvram write enable. 62 nvm_oe_n o rom/nvram output enable. table 19. rom/nvram interface
43 cs7808 6.5 video output interface this is the interface to a video encoder chip that will send the cs7808 video signals to a tv. see figure 20 . the output format is either ccir-601 or ccir-656. the cs7808 supports both master and slave config- uration. for ccir-656 mode, the cs7808 must be the sync master. in this case, the hsync and vsync pins can be redefined as gpios. . pin signal name type description 154 clk27_o o 27 mhz clock output. 159 hsync b horizontal sync. output when the cs7808 is the video master, input when the video encoder is master. 162 vsync b vertical sync. output when the cs7808 is the video mas- ter, input when the video encoder is master. 173, 172, 170, 169, 167, 166, 165, 163 vdat[7..0] o video data output[7..0] in cb,y,cr,y format. table 20. video output interface
cs7808 44 6.6 video input interface the cs7808 supports ccir-601, cif, and qcif video input format thought this interface. see table 21 . pin signal name type description 145 vin_clk i video input clock. 153 vin_vsnc i video input vertical sync. 160 vin_hsnc i video input horizontal sync. 207 vin_fld i video input field. 198, 193, 189, 184, 179, 175, 168, 164 vin_d [7..0] i video data input[7..0] in cb,y,cr,y format. table 21. video input interface
45 cs7808 6.7 audio output/input interface this is the audio pcm interface that connects to an audio codec. see table 22 . the sample rate and the size of the samples are programmable for both input and output direction. pin signal name type description 191 aud_xclk b audio 256x/384x clock input or output to serial dac. when output, is generated from cs7808 internal pll. 124 aud_bck o audio bit clock output to serial dac. 128 aud_lrck o audio out left/right clock to serial dac. 135 aud_do_0 o audio serial data out[0]. 136 aud_do_1 o audio serial data out[1]. 133 aud_do_2 o audio serial data out[2]. 177 aud_do_3 o audio serial data out[3]. 204 spdif_o o s/pdif output 137 ain_bck i audio input bit clock. the cs7808 can be programmed to use the audio output function ? s internally generated bit clock, in which case this pin is not required. 139 ain_lrck i audio input left/right clock. the cs7808 can be pro- grammed to use the audio output function ? s internally gen- erated lr clock, in which case this pin is not required. 140 ain_data i audio input data from serial adc. table 22. audio input/output interface
cs7808 46 6.8 ac97/codec interface this serial interface could be used either as a second pcm codec interface or as an ac97 serial link to an ac97 compliant codec. this interface could control a modem, or a second set of audio channels. table 23 describes the pin to signal assignments for the ac97/codec interface. pin signal name type description 142 cdc_di i serial data input from modem codec 144 cdc_do o serial data output to modem codec 146 cdc_rst o reset output to modem codec 147 cdc_ck i serial bit clock input from modem codec 148 cdc_sy b frame sync, output when cs7808 is master, input when codec is master. table 23. ac97/codec interface
47 cs7808 6.9 host master/atapi interface this 16-bit parallel host interface allows the cs7808 to be a host master, controlling other devices that would be used on the same system. see table 24 . the interface supports programmable protocols and speeds, including multiplexed and non-multiplexed addressing. slaves with different protocols can be con- nected at the same time, controlled by different chip selects. pin signal name type description 111, 115, 101, 106 h_cs[3..0] o host chip select[3..0]. the host master can be pro- grammed to use a different protocol for each of the 4 chip selects 85 h_ale o host address latch enable. used for modes which multiplex upper address information onto the data lines 92 h_rd o host read request. 93 h_wr o host write request. 95 h_rdy i host ready. connect to pull-up or pull-down if host is not used. 120 h_cko o host clock out, required for some synchronous slaves 102, 107, 97, 99, 100 h_a[4..0] o host address[4..0]. 109, 110, 112, 113, 114, 116, 117, 118, 121, 122, 123, 125, 127, 130, 132, 134 h_d[15..0] b host data bus[15..0]. these pins can also output host address during the address phase for multiplexed address/data mode. tie together to pull-up or pull-down if host is not used. table 24. host master/atapi interface
cs7808 48 6.10 general purpose input/output (gpio) the cs7808 provides 37 gpio pins, each with individual output high-z controls. high-z means that the output driver is turned off or placed in the high-impedance state. table 25 describes the general purpose i/o interface. additional pins may also be re-defined as gpio?s. pin signal name type description 26,17,4,12,8, 150, 151, 152, 155, 65, 69, 73, 77, 61, 57, 50, 47, 43, 39, 34, 30 gpio_d[20:0] b 21 general purpose i/o ? s 98, 94, 89 gpio_h[16:14] b 3 general purpose i/o ? s 149 gpio_v10 b general purpose i/o 199, 197, 196, 195, 194, 192 gpio_[15:10] b 6 general purpose i/o ? s 190, 188 gpio_[8:7] b 2 general purpose i/o ? s 195, 183, 181 gpio_[4:2] b 3 general purpose i/o ? s 174 gpio_0 b general purpose i/o table 25. general purpose i/o interface
49 cs7808 6.11 power and ground the cs7808 requires 3 different types of power supplies ? plls, internal logic and io pins -. the plls and internal logic use 2.5 v power supply, the io pins use 3.3 v power supply, and are 5 v input tolerant. (see table 26. ) pin signal name type description 1, 105, 158 vdd_pll i 2.5 v for internal plls 41, 66, 84, 108, 129, 141, 161, 178, 203 vdd_core i 2.5 v for internal core logic 20, 38, 91, 131, 180 vdd_io i 3.3 v for i/o ? s 104, 157, 208 vss_pll i ground for internal plls 36, 63, 82, 103, 126, 138, 158, 176, 200 vss_core i ground for internal core logic 18, 35, 58, 96, 119, 143, 182 vss_io i ground for i/os table 26. power and ground
cs7808 50 7. package specifications figure 16. 208-pin package drawing 1 52 53 104 105 156 157 208 0.50 0.05 0.22 0.05 30.6 0.2 28.00 0.05 28.00 0.05 30.6 0.2 detail a 0 ( min ) r0.20 1.3 0.1 r0.15 10 15 0.15 typ. 0.20 base metal with plating 0.15 typ. 0.50 0.1 5 0.2 (min) 0.35 0.1 detail a 3.35 0.05 3.80(max)
? notes

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